Gate Leakage Based Low Power Circuits

ABSTRACT

A low power voltage divider facility using gate leakage characteristics to divide voltage levels of sub-threshold and near-threshold circuits. The divider comprises a gate leakage based divider facility, and, optionally, a capacitive divider facility.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to the following:

1. Provisional Application Ser. No. 62/066,218, filed 20 Oct. 2014 (“Parent Provisional”);

2. PCT Application No. PCT/US15/50239 filed 15 Sep. 2015 (“Related Application 1”);

3. U.S. application Ser. No. 14/855,105, filed 15 Sep. 2015 (“Related Application 2”);

4. U.S. application Ser. No. [Docket No. JAM012], filed simultaneously herewith (“Related Application 3”);

5. U.S. application Ser. No. [Docket No. JAM014], file simultaneously herewith (“Related Application 4”); and

6. U.S. application Ser. No. [Docket No. JAM015], filed simultaneously herewith (“Related Application 5”).

This application claims priority to the Parent Provisional, and hereby claims benefit of the filing date thereof pursuant to 37 CFR §1.78(a)(4).

The subject matter of the Parent Provisional and the Related Applications, each in its entirety, is expressly incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to gate leakage-based (“GL-based”) circuits and more specifically, to ultra-low power, high accuracy voltage divider circuits using GL-based circuits.

2. Description of the Related Art

In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.

Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single IC, or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice.

Shown in FIG. 1 is a typical general purpose computer system 10. Although not all of the electronic components illustrated in FIG. 1 may be operable in the sub-threshold or near-threshold domains in any particular embodiment, some, at least, may be advantageously adapted to do so, with concomitant reductions in system power dissipation. In particular, in recently-developed battery-powered mobile systems, such as smart-phones and the like, many of the discrete components typical of desktop or laptop devices illustrated in FIG. 1 are integrated into a single integrated circuit chip. In the Related Applications, circuits adapted to operate in the sub-threshold domain are disclosed.

Shown by way of example in FIG. 2 is a typical single-chip microcontroller unit (“MCU”) 12 comprising: a central processing unit (“CPU”) 14; at least one random-access memory (“RAM”) facility 16; at least one voltage monitor (“VM”) facility 18; one or more timers (“Timers”) 20; at least one input/output controller (“I/O”) facility 22; at least one low dropout regulator (“LDO”) facility 24; at least one analog to digital converter (“ADC”) facility 26; a power management unit (“PMU”) 28; and a clock generator (“Clock Generator”) facility 30. A system bus (“System Bus”) 32 interconnects the several MCU facilities 14-30, and a clock distribution bus (“Clock Bus”) 34 distributes all clock signals developed by the Clock Generator 30 to the respective clocked facilities. As is known, development of the several clocks is generally controlled by information written to one or more control registers within Clock Generator 30 via the System Bus 32, and by system power state information typically provided by the PMU 28.

As is known, minimizing power is useful in low-power MCU applications. Many functions performed in a low-power MCU require various forms of voltage dividers. For example, detecting fluctuation in a power source output voltage such as a battery output or an energy harvester output is useful in low-power MCU applications. One known means of detecting these fluctuations is to continuously monitor voltage during low-power MCU operation. However, as is also known, continuous monitoring during low-power MCU operation may consume non-trivial amounts of power, due in part to large power dissipated by voltage dividers that are part of the voltage monitoring circuits. Likewise, regulators and ADCs use various forms of voltage dividers that consume power.

What is needed is a method and apparatus adapted to perform voltage division while consuming less power than known prior art.

BRIEF SUMMARY OF THE INVENTION

In one embodiment, a voltage divider facility comprising a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages, and a first capacitive facility coupled between the first and second voltages and adapted to adjust a transient behavior of the first gate-leakage based divider facility.

In another embodiment, a voltage divider facility includes a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages. The first gate leakage-based divider facility further includes a first MOS transistor adapted to receive the first voltage at a gate terminal of the first MOS transistor, and output the first divided voltage at a source and a drain terminal of the first MOS transistor, and a second MOS transistor adapted to receive the first divided voltage at a gate terminal of the second MOS transistor, and couple to a second voltage at a source and a drain terminal of the second MOS transistor. The first gate leakage-based divider facility further includes a plurality of parallel connected MOS transistors, and wherein the first gate leakage-based divider facility further includes one or more switches to select one or more of the plurality of parallel connected MOS transistors.

In another embodiment, a voltage divider facility includes a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages. The first gate leakage-based divider facility further includes a first MOS transistor adapted to receive the first voltage at a gate terminal of the first MOS transistor, and output the first divided voltage at a source and a drain terminal of the first MOS transistor, and a second MOS transistor adapted to receive the first divided voltage at a gate terminal of the second MOS transistor, and couple to a second voltage at a source and a drain terminal of the second MOS transistor. The first gate leakage-based divider facility further includes one or more switches to select one or more of the first MOS transistor and the second MOS transistor.

In another embodiment, a method for dividing a voltage comprises the steps of: [1] developing a divided voltage as a function of the voltage using a gate leakage-based divider facility; and [2] applying an adjustment function to the divided voltage using a capacitance-based divider facility.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The several embodiments may be more fully understood by a description of certain preferred embodiments in conjunction with the attached drawings in which:

FIG. 1 illustrates, in block diagram form, a general-purpose computer system adapted to instantiate any of the several embodiments;

FIG. 2 illustrates, in block diagram form, a typical integrated system adapted to practice any of the several embodiments;

FIG. 3 illustrates, in schematic form, an exemplary GL-based voltage divider facility;

FIG. 4 illustrates, in schematic form, exemplary modified forms of the GL-based voltage divider facility illustrated in FIG. 3, or exemplary modified forms of the gate leakage resistive element illustrated in FIG. 15;

FIG. 5 illustrates, in schematic form, an exemplary GL-based voltage divider facility with selectable divide ratio;

FIG. 6 illustrates, in schematic form, an exemplary GL-based voltage divider facility with selectable device sizes;

FIG. 7 illustrates, in schematic form, an exemplary GL-based voltage divider facility with selectable divide ratio;

FIG. 8 illustrates, in schematic form, an exemplary GL-based voltage divider facility with selectable device sizes;

FIG. 9 illustrates, in partial block diagram form and partial schematic form, a voltage monitor facility adapted to practice any of the several embodiments;

FIG. 10 illustrates, in partial block diagram form and partial schematic form, a voltage monitor facility adapted to practice any of the several embodiments;

FIG. 11 illustrates, in partial block diagram form and partial schematic form, a low dropout regulator facility adapted to practice any of the several embodiments;

FIG. 12 illustrates, in block diagram form, an amplifier adapted to practice any of the several embodiments;

FIG. 13 illustrates, in block diagram form, an analog-to-digital converter adapted to practice any of the several embodiments;

FIG. 14 illustrates, in schematic form, a voltage ladder adapted to practice any of the several embodiments;

FIG. 15 illustrates, in block diagram form and partial schematic form, a current reference generator facility adapted to operate in accordance with some embodiments;

FIG. 16 illustrates, in schematic form, a tunable gate leakage resistive facility;

FIG. 17 illustrates, in schematic form, a tunable current mirror facility;

FIG. 18 illustrates, in schematic form, another embodiment of exemplary voltage divider facility with selectable device sizes illustrated in FIG. 6; and

FIG. 19 illustrates, in schematic form, another exemplary voltage divider facility with selectable devices sizes and selectable capacitor sizes.

In the drawings, similar elements will be similarly numbered whenever possible. However, this practice is simply for convenience of reference and to avoid unnecessary proliferation of numbers, and is not intended to imply or suggest that identity is required in either function or structure in the several embodiments.

DETAILED DESCRIPTION

FIG. 3 illustrates, in schematic form, a voltage divider facility 36 adapted to operate in accordance to some embodiments. According to one embodiment, the voltage divider facility 36 includes a GL-based voltage divider facility 38 and a capacitive facility 40.

In the illustrated embodiment, the GL-based voltage divider facility 38 includes a stack of transistors that includes, in this simple example, a first transistor 42 and a second transistor 44. The first transistor 42 has its gate terminal coupled to a measured voltage 46, here labeled as “VMEAS”, and has both source and drain terminals shorted together. Alternatively, in a taller stack, the gate terminal of the first transistor 42 may be coupled to the measured voltage 46 via one or more additional transistors (see, e.g., FIG. 14). The shorted source and drain terminals of the first transistor 42 are coupled to the gate terminal of the second transistor 44. The gate terminal of the second transistor 44 is also coupled to the intermediate node 48, labeled here as “VDIV”. The intermediate node 48 “VDIV” is operable as a divided version of the measured voltage “VMEAS” 46. The source and drain terminals of the second transistor 44 are, in this example, coupled to a ground node. In a different embodiment, the source and drain terminals of the second transistor 44 may be coupled to a node a voltage other than the ground voltage. For example, the source and drain terminals of the second transistor 44 may be coupled to the gate of still another transistor (see, e.g., FIG. 14) in a taller stack. The bulk or well of each transistor may either be tied to a constant body bias voltage or shorted to source/drain of the respective devices. According to some embodiments, the bulk of the transistors are connected to their respective source/drain terminals. As is known, capacitance is related to the threshold voltage of the transistors (“Vth”) and Vth is related to body bias.

In the illustrated embodiment, the capacitive facility 40 includes a stack of compensation capacitors including, in this simple example, a first compensation capacitor 50 and a second compensation capacitor 52. As is known, and according to other embodiments, capacitive facility 40 may comprise a single capacitive element (not shown) or more than the two illustrated capacitive elements (not shown). As is also known, these capacitive elements may be actual capacitors, MOSFETs, MoM capacitors, MiM capacitors, or any other means that would be understood by one of ordinary skill in the art. The leakage current of the capacitive element is significantly less than the leakage current of the gate oxides, thus ensuring that the capacitors affect only the AC coupling and do not affect DC current levels. The first compensation capacitor 50 has one of its terminals or plates coupled to the measured voltage 46 and its other terminal or plate coupled to the intermediate node 48. The second compensation capacitor 52 has one of its terminals or plates coupled to the intermediate node 48, and its other terminal or plate coupled to the ground node.

During operation, the divided version, “VDIV”, of the measured voltage “VMEAS” 46 is developed as a function of the GL-based voltage divider facility 38 and the capacitive facility 40. Generally, as is known, current is conducted through the gate oxide of the transistors. According to one embodiment, thin-oxide native devices are utilized in the GL-based voltage divider facility. As is known, these devices are always on and will constitute a constant capacitance value. A voltage level commiserate with a target technology is applied at the gate of the first transistor 42, i.e., the uppermost oxide of the first transistor 42. This in turn develops a voltage across the first oxide causing charge to tunnel through the oxide, thus developing current. This current charges the oxide layers of subsequent devices until all oxides in the stack have substantially identical current flowing through each device. According to one embodiment, the gate-oxides of the devices are substantially identical and, consequently, the voltages across all oxides are substantially identical. Thus, according to this embodiment, the circuit acts as a voltage divider. As is known by one of ordinary skill in the art of circuit design, the small leakage current through the oxide emulates a high-value resistor, with voltage division corresponding to a ratio of oxide leakage as determined by stacking, relative oxide thicknesses and relative oxide areas.

GL-based voltage divider facility 38 illustrated in FIG. 3 is of particular interest. As discussed earlier, GL-based voltage divider facility 38 includes a stack of at least two transistors tied in a gate-leakage configuration. While VMEAS is fluctuating at low frequency, the voltage division is achieved using the GL-based voltage divider facility 38. At 130 nm process technology and lower, leakage current through the gate oxide has become non-negligible, i.e., the leakage current has even become comparable to or greater than sub-threshold leakage current. Gate leakage current is therefore usable in current division structures like the GL-based voltage divider facility 38 illustrated in FIG. 3. For low power voltage dividers, gate leakage current may be more attractive than sub-threshold leakage current due to its relatively low process and temperature dependence. Sub-threshold leakage current is exponentially sensitive to temperature and threshold voltage variations, so currents can become dangerously low at low temperature and prohibitively high at high temperature. In general, gate leakage current remains relatively stable across temperature and process, and thus requires substantially less tuning than sub-threshold leakage current.

Though gate leakage current can be extremely low, it does not react quickly to high frequency fluctuations on VMEAS. However, at high frequencies the capacitive characteristics of the GL-based voltage divider facility 38 overtake the resistive divide action of the same transistor stack. Each transistor in the stack looks electrically like a capacitor at high frequency and thus acts as a capacitive divider instead of a resistive divider. Consequently, the divider has good response times at both high and low frequencies.

Due to the effects of parasitic capacitances and the non-linear capacitive behavior of the GL-based voltage divider facility 38 illustrated in FIG. 3, capacitive facility 40 is placed in parallel with the GL-based voltage divider facility 38. The capacitive facility 40 adjusts the transient behavior of the GL-based voltage divider facility 38, thus enabling better linearity, or smoothing, of intermediate node 48 “VDIV” across process, temperature and voltage. The relatively small gate leakage of the transistors in the divider can typically compensate for noise with bandwidth of tens or hundreds of Hertz but are unable to maintain a correct divide ratio at higher frequencies. The compensating capacitors are typically valuable in compensating for transient behavior at bandwidths of thousands of Hertz and above. As illustrated in FIG. 3, one capacitor can be placed in parallel with each transistor. Alternatively, according to another embodiment, one or more capacitors may be placed in parallel with multiple transistors to save area.

FIG. 4 illustrates, in schematic form, exemplary alternative forms of the GL-based voltage divider facility 38 shown in FIG. 3 according to some embodiments. Various combination of transistor types, i.e., NMOS, PMOS, etc., may comprise the GL-based voltage divider facility 38. The performance of the circuit, and the associated value of the divided voltage node 48, is a function of sufficient gate leakage current through the GL-based voltage divider facility 38. According to one embodiment, sufficient gate leakage may be characterized as on the order of greater than 1 pA. In particular, as illustrated in FIG. 3, the GL-based voltage divider facility 38 may include a combination of only NMOS devices, including NMOS device 42 and NMOS device 44. According to a different embodiment, FIG. 4(a) illustrates a combination of PMOS devices including PMOS device 54 and PMOS device 56 that are a suitable substitute for the NMOS devices included in the GL-based voltage divider facility 38 illustrated in FIG. 3. According to a different embodiment, FIG. 4(b) illustrates a combination of both NMOS and PMOS devices connected in parallel and series, including NMOS device 58, NMOS device 60, PMOS device 62 and PMOS device 64, that are a suitable substitute for the NMOS devices included in the GL-based voltage divider facility 38 illustrated in FIG. 3. According to yet a different embodiment, FIG. 4(c) illustrates a single NMOS and a single PMOS devices connected in series, including NMOS device 66 and PMOS device 68, that are a suitable substitute for the NMOS devices included in the GL-based voltage divider facility 38 illustrated in FIG. 3. Other configurations that provide the requisite performance are anticipated.

According to some embodiments, it may be desirable to alter selectively the divide ratio of the GL-based voltage divider facility 38 illustrated in FIG. 3. For yield purposes, it can be useful to support post-silicon tuning/calibration of the number of transistors in the stack and the relative sizes of the transistors. Accordingly, it may be desirable, in some embodiments, to alter selectively the number of transistors in the GL-based voltage divider facility 38 illustrated in FIG. 3. FIG. 5 illustrates, in schematic form, an exemplary voltage divider facility 70 with selectable divide ratio adapted according to some embodiments. The voltage divider facility 70 includes a GL-based voltage divider facility 38′ and the tunable capacitive facility 40′. The GL-based divider facility 38′ includes the stack of at least two transistors that includes the first transistor 42, the second transistor 44, a first switch 72, and a second switch 74. The tunable capacitive facility 40′ includes the stack of at least two compensation capacitors including a first compensation capacitor 50 and a second compensation capacitor 52. The tunable capacitive facility 40′ also includes a third switch 73 and a fourth switch 75. Stacks with more than two transistors or more than two compensation capacitors may also have additional switches to alter the divide ratio.

During operation, the selected number of transistors in the GL-based divider facility 38′ alters the divide ratio and concomitantly the voltage value of the divided voltage 48. By way of example, closing the first switch 72 bypasses and effectively eliminates the first transistor 42 from the GL-based divider facility 38′. Likewise, closing the second switch 74 bypasses and effectively eliminates the second transistor 44 from the GL-based divider facility 38′. In this way, the divide ratio is selectively altered, effectively allowing a single circuit to monitor different voltage levels. Similarly, first compensation capacitor 50 and second compensation capacitor 52 may be selectively added or removed from tunable capacitive facility 40′ through the use of third switch 73 and fourth switch 75. These switches, i.e., the first switch 72, the second switch 74, the third switch 73, and the fourth switch 75 may each be implemented using pass transistors or transmission gates, embodiments of which are well known to one of ordinary skill in the art of circuit design. Selectively altering the divide ratio may be controlled via software means, by hardware means, i.e., hardware fuses or non-volatile memory, or by any other means known to one of ordinary skill in the art of circuit design.

As is known, the effects of process variation on effective transistor size may impact the divide ratio of the GL-based voltage divider facility 38 illustrated in FIG. 3, and unpredictably alter the divide ratio. Therefore, according to some embodiments, it may also be desirable to alter selectively the sizes of the transistors of the GL-based voltage divider facility 38 illustrated in FIG. 3. This selective alteration is known in the art as tuning. Such transistor size tuning may act to minimize the effects of process variation. FIG. 6 illustrates, in block diagram form, an exemplary voltage divider facility 76 with selectable device sizes according to some embodiments. Voltage divider facility 76 includes a GL-based voltage divider facility 38″ and the capacitive facility 40. Note that capacitive facility 40 may be replaced by capacitive facility 40′ of FIG. 5. The GL-based voltage divider facility 38″ includes the stack of at least two transistors that includes the first transistor 42 and the second transistor 44. The first transistor 42 is illustrated as at least three (3) selectable parallel-coupled transistors that include transistor 42 a, transistor 42 b, and transistor 42 c. The GL-based voltage divider facility 38″ also includes a first switch 78, a second switch 80, and a third switch 82, each of which may selectively enable one of the at least three (3) selectable parallel transistors respectively. As one of ordinary skill in the art of integrated circuit design will understand, any number of parallel transistors (i.e. two or more) may be suitable to achieve proper tuning

During operation, the effective size of the first transistor 42 may be modified to compensate for the prior mentioned process variation effects, thus altering or tuning the divide ratio of the GL-based voltage divider facility 38″, and concomitantly the voltage value of the divided voltage 48. By way of example, closing the first switch 78 and connecting transistor 42 a into the circuit. Likewise, closing the second switch 80 connects transistor 42 b in parallel with transistor 42 a, and closing the third switch 82 connects transistor 42 c in parallel with transistors 42 a and 42 b. As is understood by one of ordinary skill in the art of circuit design, various combinations of transistor sizes may be used in different device size tuning methodologies, i.e., linear, binary-weighted, etc.

According to another embodiment, an adjustment to the transient behavior of intermediate node 48 “VDIV” is not needed and the capacitive facility, illustrated and discussed previously, is accordingly not needed. FIG. 7 illustrates, in schematic form, an exemplary voltage divider facility 84 with selectable divide ratio according to some embodiments. The voltage divider facility 84 includes a GL-based voltage divider facility 38′. The GL-based voltage divider facility 38′ includes the stack of at least two transistors that includes the first transistor 42, the second transistor 44, a first switch 72, and a second switch 74. During operation, the GL-based voltage divider facility 38′ operates in a substantially similar manner as previously described above.

Similarly, FIG. 8 illustrates, in schematic form, an exemplary voltage divider facility 86 with selectable device sizes wherein the transient behavior of intermediate node 48 “VDIV” is not needed and the capacitive facility, illustrated and discussed previously, is accordingly not needed. Voltage divider facility 86 includes a GL-based voltage divider facility 38″. The GL-based voltage divider facility 38″ includes the stack of at least two transistors that includes the first transistor 42 and the second transistor 44. The first transistor 42 is illustrated as at least three (3) selectable parallel-coupled transistors that include transistor 42 a, transistor 42 b, and transistor 42 c. The GL-based voltage divider facility 38″ also includes a first switch 78, a second switch 80, and a third switch 82, each of which may selectively enable one of the at least three (3) selectable parallel transistors respectively. During operation, the GL-based voltage divider facility 38″ operates in a substantially similar manner as previously described above.

FIG. 9 illustrates, in partial block diagram form and partial schematic form, a voltage monitor facility 88 adapted to practice any of the several embodiments. Voltage monitor facility 88 includes the GL-based voltage divider facility 38, the capacitive facility 40, a comparator 90, and a reference voltage generator 92. In the illustrated embodiment, divided voltage “VDIV” 48 is coupled to one input of the comparator 90 and the output of reference voltage generator 92 is coupled to the other input of the comparator 90. During operation, the divided voltage 48 is compared against the output of reference voltage generator 92 utilizing the comparator 90. In accordance with some embodiments, the output of the comparator 90 indicates whether the measured voltage “VMEAS” 46 is above or below the output of the reference voltage generator 92. The comparator 90 and the reference voltage generator 92 circuits illustrated in FIG. 9 may be constructed using any techniques known to one of ordinary skill in the art of circuit design. However, for low power applications, it is beneficial to implement both structures using sub-threshold or near-threshold circuits. Other configurations are anticipated.

FIG. 10 illustrates, in partial block diagram form and partial schematic form, a voltage monitor facility 94 adapted to practice any of the several embodiments. As discussed previously, an adjustment to the transient behavior of intermediate node 48 “VDIV” is not needed and the capacitive facility, illustrated and discussed previously, is accordingly not needed. Voltage monitor facility 94 includes the GL-based voltage divider facility 38, the comparator 90, and a reference voltage generator 92. In the illustrated embodiment, divided voltage “VDIV” 48 is coupled to one input of the comparator 90 and the output of reference voltage generator 92 is coupled to the other input of the comparator 90. During operation, the divided voltage 48 is compared against the output of reference voltage generator 92 utilizing the comparator 90. In accordance with some embodiments, the output of the comparator 90 indicates whether the measured voltage “VMEAS” 46 is above or below the output of the reference voltage generator 92. The comparator 90 and the reference voltage generator 92 circuits illustrated in FIG. 10 may be constructed using any techniques known to one of ordinary skill in the art of circuit design. However, for low power applications, it is beneficial to implement both structures using sub-threshold or near-threshold circuits. Other configurations are anticipated.

FIG. 11 illustrates, in block diagram form, a low-dropout regulator (“LDO”) facility 96 adapted to practice any of the several embodiments. LDO facility 96 includes a reference voltage generator 98, a comparator 100, a PMOS transistor 102, and a voltage divider facility 104 adapted to practice any of the several embodiments. In the illustrated embodiment, the output of reference voltage generator 98 is coupled to one input of the comparator 100 and GL-based voltage divider 104 is coupled to the other input of the comparator 100. The output of comparator 100 is coupled to the gate terminal of the PMOS transistor 102. The source terminal of the PMOS transistor 102 is coupled to VDD and the drain terminal of the PMOS transistor is coupled to the input of the GL-based voltage divider 104. As is known, according to some embodiments, voltage divider facility 104 is used in a feedback loop of an error amplifier to set an output voltage value, here illustrated as “VREG”.

FIG. 12 illustrates, in block diagram form, an amplifier 106 adapted to practice any of the several embodiments. Amplifier 106 includes a comparator 108 and a voltage divider facility 110 adapted to practice any of the several embodiments. In the illustrated embodiment, one input of the comparator 108 is coupled to a input, here illustrated as “VIN”, and the other input the comparator 108 is coupled to the output of the voltage divider facility 110. The output of the comparator 108 is coupled to the input of the voltage divider facility 110 and to the output, here illustrated as “VOUT”. According to some embodiments, voltage divider facility 110 is used in a feedback loop of the error amplifier circuit 106 to set a gain value. As is known, the amplifier facility 106 may be used to apply gain to a voltage input for a variety of circuits including analog-to-digital converters, illustrated in FIG. 13, and oscillators.

FIG. 14 illustrates, in schematic form, a voltage ladder 116 adapted to practice any of the several embodiments. Voltage ladder 116 includes transistors 118, 120, and 122 and operates in a substantially similar manner as that described previously. Here, however, rather than providing a single voltage from the voltage divider, more than the single output voltage is provided. In the illustrated embodiment, the output voltage illustrated as “VOUT1” is provided from the circuit node between transistor 118 and 120. The output voltage illustrated as “VOUT2” is provided from the circuit node between transistors 120 and 122. Other embodiments are anticipated.

As is known, gate leakage is minimally dependent upon temperature. As such, in addition to being useful for voltage dividers, gate leakage based circuits may also be used as current reference generators with reasonably good temperature tolerance. FIG. 15 illustrates, in block diagram form and partial schematic form, a current reference generator facility 124 adapted to operate in accordance with some embodiments. The current reference generator facility 124 includes a reference voltage generator 126, an analog voltage buffer 128 a current mirror 130, a gate leakage resistive element 132, and a load element 134. The analog voltage buffer 128 includes a comparator 136 and a transistor 138. The current mirror 130 includes transistor 140 and transistor 142. As is understood by one of ordinary skill in the art of circuit design, the voltage reference generator 126 is coupled to the analog voltage buffer 128, providing a stable reference voltage to the analog voltage buffer 128. In turn, the analog voltage buffer 128 may apply some gain to the reference voltage. As is understood, the analog voltage buffer 128 is coupled to the GL-based resistive element 132 and provides a stable voltage to one terminal of the GL-based resistive element 132. With a stable voltage across the GL-based resistive element 132, a stable reference current, here labeled I_(bias), is available. The analog voltage buffer 128 is also coupled to the current mirror 130. As is understood, the current mirror 130 is adapted to copy the current, here labeled I_(out), for use in load 134.

In accordance with some embodiments, the GL-based resistive element 132 may be implemented using various configurations of NMOS and/or PMOS devices. According to one embodiment as illustrated in FIG. 15, a single NMOS device may be used as the GL-based resistive element 132. Similarly, according to a different embodiment, a single PMOS device (not shown) may be used as the GL-based resistive element 132. Referring to FIG. 4, several other alternative embodiments of the GL-based resistive element 132 are illustrated. For example, the GL-based resistive element may be implemented as a set of series connected devices (see, FIG. 4(a)), a set of series-parallel connected devices (see, FIG. 4(b)), or a mix of series connected devices (see, FIG. 4(c)). Other configurations of devices that provide current dominated by gate leakage are anticipated.

Referring back to FIG. 15, according to one embodiment, the analog voltage buffer 128 can apply a voltage to the top of the gate leakage resistive element 132. According to a different embodiment (not shown), the analog voltage buffer 128 can apply a voltage to the bottom of the gate leakage resistive element 132. According to yet a different embodiment (not shown), two separate analog voltage buffers may be used to apply two separate voltages, one voltage to the top of and one voltage to the bottom of the gate leakage resistive element 132. In this case, the voltage reference generator 126 must supply two reference voltages.

The current mirror 130, illustrated in FIG. 15, may be constructed using any known mirroring technique known to one of ordinary skill in the art of circuit design. FIG. 15 illustrates one simple instance of the current mirror 130 that may be sufficient in some embodiments. Other configurations of current mirrors are anticipated.

As discussed earlier in this application, process variations may impact the effective transistor size of GL-based elements. As is known, one method of compensating for process variations is to selectively alter, or tune, the sizes of the transistors comprising the particular devices of interest. FIG. 16 illustrates, in schematic form, a tunable gate leakage resistive facility 144 according to some embodiments. Tunable gate leakage resistive element 144 includes transistor 132 a, transistor 132 b, transistor 132 c, switch 146, switch 148, and switch 150.

During operation the size of the tunable gate leakage resistive facility 144 may be modified to compensate for the prior-mentioned process variation effects. By way of example, closing the first switch 146 connects transistor 132 a into the circuit. Likewise, closing the second switch 148 connects transistor 132 b in parallel with transistor 132 a, and closing the third switch 150 connects transistor 132 c in parallel with transistors 132 a and 132 b. As is understood by one of ordinary skill in the art of circuit design, various combinations of transistor sizes may be used in different device size tuning methodologies, i.e., linear, binary-weighted, etc.

FIG. 17 illustrates, in schematic form, a tunable current mirror facility 152 according to some embodiments. Tunable current mirror facility 152 includes transistor 140 a, transistor 140 b, transistor 140 c, transistor 142, switch 154, switch 156, and switch 158. During operation, the size of the tunable current mirror facility 152 may be modified to compensate for the prior mentioned process variation effects. By way of example, closing the first switch 154 connects transistor 146 a into the circuit. Likewise, closing the second switch 156 connects transistor 146 b in parallel with transistor 146 a, and closing the third switch 158 connects transistor 146 c in parallel with transistors 146 a and 146 b. As is understood by one of ordinary skill in the art of circuit design, various combinations of transistor sizes may be used in different device size tuning methodologies, i.e., linear, binary-weighted, etc.

Generally, as is understood, the temperature coefficient of the reference voltage generator 92 or reference voltage generator 126 will set to be close to 0, i.e., the output voltage will be stable across temperature. However, gate leakage has a small temperature dependence. This dependence may be compensated with a positive to absolute temperature (“PTAT”) or complimentary to absolute temperature (“CTAT”) characteristic on the voltage reference generator 92 or reference voltage generator 126. Consequently, an implementation according to some embodiments may include a voltage reference generator with a CTAT or PTAT characteristic. The analog voltage buffer may also apply the temperature compensation if its gain value has a CTAT or PTAT characteristic.

FIG. 18 illustrates, in schematic form, another embodiment of exemplary voltage divider facility with selectable device sizes illustrated in FIG. 6. Voltage divider facility 76′ includes a GL-based voltage divider facility 38′″ and the capacitive facility 40. The GL-based voltage divider facility 38′″ includes the stack of at least two transistors that includes the first transistor 42 and the second transistor 44. The first transistor 42 is illustrated as at least three (3) selectable parallel-coupled transistors that include transistors 42 a, 42 b, and 42 c and switches 78, 80, and 82. The second transistor 44 is illustrated as at least three (3) selectable parallel-coupled transistors that include transistors 44 a, 44 b, and 44 c and switches 79, 81, and 83. This embodiment operates substantially similar to FIG. 6, as described above.

FIG. 19 illustrates, in schematic form, another exemplary voltage divider facility with selectable devices sizes and selectable capacitor sizes. Voltage divider facility includes a GL-based voltage divider facility 38″, previously described and illustrated in FIG. 18, and capacitive facility 40″. In the illustrated embodiment, the capacitive facility 40″ includes a stack of compensation capacitors including a first compensation capacitor 50 and a second compensation capacitor 52. The first compensation capacitor 50 is illustrated as at least three (3) selectable parallel-coupled capacitors that include capacitor 50 a, 50 b, and 50 c and switches 85, 87, and 89. The second compensation capacitor 52 is illustrated as at least three (3) selectable parallel-coupled capacitors that include capacitors 52 a, 52 b, and 52 c and switches 91, 93, and 95. During operation, the size of the first capacitor 50 may be modified to compensate for the prior mentioned process variation effects. By way of example, closing the first switch 85 connects capacitor 50 a into the circuit. Likewise, closing the second switch 87 connects capacitor 50 b in parallel with capacitor 50 a, and closing the third switch 89 connects capacitor 50 c in parallel with capacitors 50 a and 50 b. Each successive addition of a parallel-coupled capacitor increases the overall value of capacitor 50. Similar tuning may be performed on capacitor 52 via opening and/or closing switches 91, 93, and 95. As is understood by one of ordinary skill in the art of circuit design, various combinations of capacitor sizes may be used in different device size tuning methodologies, i.e., linear, binary-weighted, etc.

Although described in the context of particular embodiments, one of ordinary skill in this art will readily realize that many modifications may be made in such embodiments to adapt either to specific implementations.

Thus it is apparent that an improved method and apparatus to voltage division with increased accuracy while consuming less power than known prior art has been disclosed. Further, the method and apparatus provides performance generally superior to the best prior art techniques. 

What is claimed is:
 1. A voltage divider facility comprising: a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages; and a first capacitive facility coupled between the first and second voltages and adapted to adjust a transient behavior of the first gate-leakage based divider facility.
 2. The voltage divider facility of claim 1 wherein said first gate leakage-based divider facility further comprises: a first MOS transistor adapted to: receive said first voltage at a gate terminal of said first MOS transistor; and output said first divided voltage at a source and a drain terminal of said first MOS transistor; a second MOS transistor adapted to: receive said first divided voltage at a gate terminal of said second MOS transistor; and couple to a second voltage at a source and a drain terminal of said second MOS transistor.
 3. The voltage divider facility of claim 2 wherein said first MOS transistor and said second MOS transistor are of type NMOS.
 4. The voltage divider facility of claim 2 wherein said first MOS transistor and said second MOS devices are of type PMOS.
 5. The voltage divider facility of claim 2 wherein said first MOS transistor is of type NMOS and said second MOS device is of type PMOS.
 6. The voltage divider facility of claim 2 wherein said first MOS transistor is of type PMOS and said second MOS device is of type NMOS.
 7. The voltage divider facility of claim 2 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said first MOS transistor and said second MOS transistor.
 8. The voltage divider facility of claim 2 wherein said first MOS transistor is further characterized as comprising a plurality of parallel connected MOS transistors.
 9. The voltage divider facility of claim 8 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.
 10. The voltage divider facility of claim 2 wherein said second MOS transistor is further characterized as comprising a plurality of parallel connected MOS transistors.
 11. The voltage divider facility of claim 10 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.
 12. The voltage divider facility of claim 2 wherein said first MOS transistor and said second MOS transistor are further characterized as comprising a plurality of parallel connected MOS transistors.
 13. The voltage divider facility of claim 12 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.
 14. The voltage divider facility of claim 1 wherein said first capacitive facility further comprises: a first capacitor adapted to: receive said first voltage at a first terminal of said first capacitor; and output said first divided voltage at a second terminal of said first capacitor; a second capacitor adapted to: receive said first divided voltage at a first terminal of said second capacitor; and couple to a second voltage at a second terminal of said second capacitor.
 15. The voltage divider facility of claim 14 wherein said first capacitor is further characterized as comprising a plurality of parallel connected capacitors.
 16. The voltage divider facility of claim 15 wherein said first capacitive facility further comprises one or more switches to select one or more of said plurality of parallel connected capacitors.
 17. The voltage divider facility of claim 14 wherein said second capacitor is further characterized as comprising a plurality of parallel connected capacitors.
 18. The voltage divider facility of claim 17 wherein said first capacitive facility further comprises one or more switches to select one or more of said plurality of parallel connected capacitors.
 19. The voltage divider facility of claim 14 wherein said first capacitor and said second capacitor are further characterized as comprising a plurality of parallel connected capacitors.
 20. The voltage divider facility of claim 19 wherein said first capacitive facility further comprises one or more switches to select one or more of said plurality of parallel connected capacitors.
 21. An electrical facility comprising a voltage divider facility according to claim
 1. 22. The electrical facility of claim 21 further characterized as a low dropout regulating facility.
 23. The electrical facility of claim 21 further characterized as an analog to digital conversion facility.
 24. The electrical facility of claim 21 further characterized as a voltage monitor facility.
 25. The electrical facility of claim 24 wherein said voltage monitoring facility further comprises: a first reference voltage generator adapted to output a first reference voltage; and a first comparator adapted to: receive said first divided voltage; receive said first reference voltage; and compare said first divided voltage to said first reference voltage, and, in response, to output: a logic_1 value if said first divided voltage is greater than said first reference voltage; and a logic _0 value if said first divided voltage is not greater than said first reference voltage.
 26. A voltage divider facility comprising: a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages; wherein said first gate leakage-based divider facility further comprises: a first MOS transistor adapted to: receive said first voltage at a gate terminal of said first MOS transistor; and output said first divided voltage at a source and a drain terminal of said first MOS transistor; a second MOS transistor adapted to: receive said first divided voltage at a gate terminal of said second MOS transistor; and couple to a second voltage at a source and a drain terminal of said second MOS transistor; wherein said first gate leakage-based divider facility further comprises a plurality of parallel connected MOS transistors; and wherein the first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.
 27. A voltage divider facility comprising: a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages; wherein said first gate leakage-based divider facility further comprises: a first MOS transistor adapted to: receive said first voltage at a gate terminal of said first MOS transistor; and output said first divided voltage at a source and a drain terminal of said first MOS transistor; a second MOS transistor adapted to: receive said first divided voltage at a gate terminal of said second MOS transistor; and couple to a second voltage at a source and a drain terminal of said second MOS transistor; and wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said first MOS transistor and said second MOS transistor.
 28. A method for dividing a voltage, the method comprising the steps of: [1] developing a divided voltage as a function of said voltage using a gate leakage-based divider facility; and [2] applying an adjustment function to said divided voltage using a capacitance-based divider facility.
 29. The method of claim 28 wherein said method further comprises the step of: [3] selectively tuning a number of series connected transistor devices in said gate leakage-based divider facility.
 30. The method of claim 29 wherein said method further comprises the step of: [4] selectively tuning a number of parallel connected transistors devices in said gate leakage-based divider facility.
 31. The method of claim 28 wherein said method further comprises the step of: [3] selectively tuning a number of parallel connected transistors devices in said gate leakage-based divider facility.
 32. An electrical facility configured to perform the steps of a method according to any one of claims 28 to
 31. 33. The electrical facility of claim 32 further characterized as a low dropout regulating facility.
 34. The electrical facility of claim 32 further characterized as an analog to digital conversion facility.
 35. The electrical facility of claim 32 further characterized as a voltage monitor facility.
 36. An electronic system comprising an electrical facility according to claims 32 to
 35. 37. A computer readable medium including executable instructions which, when executed in a processing system, causes the processing system to perform the steps of a method according to any one of claims 28 to
 31. 